1. Technical Field
The present invention relates to an I/O cell capable of finely controlling drive strength.
2. Description of Related Art
A semiconductor integrated circuit device transmits and receives data to and from other external apparatuses using input/output circuits (also referred to as ‘I/O cells’). An output cell in the I/O cell includes a drive circuit for loading a sufficient volume of data on an output pad and an ESD protection circuit for preventing a high voltage generated from an exterior from being transferred into the I/O cell or to the drive circuit.
FIG. 1 is a block circuit diagram illustrating a configuration of an I/O cell according to a related art.
Referring to FIG. 1, an output signal coming from terminal 12 is input into a drive circuit 20 through two inverters 14 and 16. Since the output signal of terminal 12 passes through two inverters 14 and 16, an output of inverter 16 has the same data value as the output signal of terminal 12, but its current capacity is higher than that of the output signal of terminal 12. The output of inverter 16 is input into a drive circuit 20. Drive circuit 20 is comprised of a pull-up transistor PC1 (PMOS transistor) pulling a voltage level on an output pad 40 up to a power supply voltage VDD and a pull-down transistor NC1 (NMOS transistor) pulling a voltage level of output pad 40 down to a ground voltage. Both transistors are being connected in the form of an inverter structure. That is, when the output signal on terminal 12 is “0”, pull-up transistor PC1 is turned on, such that output pad 40 is connected to the power supply voltage. When the output signal on terminal 12 is “1”, pull-down transistor NC1 is turned on, such that output pad 40 is connected to the ground voltage terminal.
I/O cell 10 typically has a separate electrostatic protection circuit 30, although, drive circuit 20 in I/O cell 10 may be adapted for electrostatic protection. Electrostatic protection circuit 30 includes a PMOS transistor PC2 connected as a diode between output pad 40 and power supply VDD; and a NMOS transistor NC2 connected as a diode between output pad 40 and the ground voltage terminal. Accordingly, PMOS transistor PC2 protects drive circuit 20 when a voltage signal higher than the power supply voltage is applied to output pad 40; and NMOS transistor NC2 protects drive circuit 20 when a voltage signal much lower than the ground voltage is applied to output pad 40.
When an electrostatic voltage is applied to output pad 40, drive circuit 20 as well as electrostatic protection circuit 30 enables the electrostatic signal to flow to VDD or the ground through PMOS transistor PC1 or NMOS transistor NC1, thereby, protecting the semiconductor integrated circuit from static electricity. Such an I/O cell 10 is called a self protection I/O cell 10. Since all transistors in self protection I/O cell 10 have to serve for the electrostatic protection, the size of the transistors should be a predetermined level or higher (both in width and length). A transistor whose size is the minimum level is called “a basic transistor” in this specification.
In order to make drive strength of self protection I/O cell 10 diverse, it should control the number of pull-up transistor PC1 and pull-down transistor NC1. For example, assuming that 10 basic transistors are prepared and the drive strength of the basic transistor is 2 mA; when the drive strength of I/O cell 10 is 4 mA, the drive circuit is formed of 2 basic transistors and the remaining 8 basic transistors are grounded and not used.
Therefore, the conventional self protection I/O cell has a shortcoming in that there is no alternative other than to control the drive strength as a multiple of the strength of the basic transistor. For example, when drive strength of a basic transistor that can constitute the pull-up transistor and the pull-down transistor is 2 mA, the drive strength can be extended only in an integer multiple of the basic strength in the art, such as 4 mA, 6 mA, 8 mA, and so on. Further, since an SoC (System on Chip) device used in mobile equipment require a variety of voltages depending on various operation modes (for example, sleep mode, normal mode, highest speed operation mode, etc.), the I/O cell should be able to control the drive strength correspondingly to the requirements. However, it is very difficult for the conventional I/O cell to control the drive strength in diverse and fine manners.